At present, along with increased demand for high-capacity data transmission, a high-speed digital synchronous-transmission system has been spreading rapidly. Representative standards of the digital synchronous-transmission system are Synchronous Digital Hierarchy (SDH) defined by the International Telecommunication Union, Telecommunication Standardization Sector (ITU-T), and Synchronous Optical Network (SONET) defined by the American National Standards Institute (ANSI). Both standards define configurations of optical synchronous-communication systems and functions of transmission devices.
In the digital synchronous-transmission systems using SDH and SONET, there is generally used a synchronous multiple signal having a signal called “overhead” to perform monitoring and maintenance of a transmission device and a communication network, added to a main signal portion obtained by multiplexing a digitalized main signal.
Some of the digital synchronous-transmission systems employ “1+1 APS (Automatic Protection Switch)” function that achieves control of switchover from a currently-used line to an auxiliary line when a fault occurs in a network configured by a Bidirectional Line Switched Ring (BLSR) system that connects between transmission devices with a ring-shaped line of the currently-used line or the auxiliary line. By mapping APS byte (K1 byte or K2 byte) in an overhead of a synchronous multiplexed signal, when a fault occurs in the currently-used line, switchover control is performed to switch a system to a redundant system of automatically switching a transmission path from the currently-used line to the auxiliary line.
An outline of a switching process to a redundant system in a network configuration of the BLSR is briefly explained with reference to FIGS. 17A and 17B to FIGS. 20A and 20B. FIGS. 17A and 17B are schematic diagrams for explaining a switchover process of switching to a redundant system in the network configuration of the BLSR. FIG. 18 is a schematic diagram for explaining a configuration of a centralized CPU device. FIG. 19 is a schematic diagram for explaining a configuration of a distributed CPU device. FIGS. 20A and 20B are schematic diagrams for explaining problems of a conventional technique.
In the network configuration of the BLSR, in a normal operation state, a path in only one direction (either a clockwise direction or a counterclockwise direction) is used as a communication path of an optical signal. When a communication fault occurs, the path is switched to a path in a direction (an auxiliary side) opposite to the direction of the path used in the normal operation, thereby quickly responding to a line fault. For example, as illustrated in FIG. 17A, it is assumed that in a normal operation state, an optical signal from Node 4 to Node 2 is transmitted in a clockwise direction using a path via Node 3, in a ring network in which four optical transmission devices of Node 1 to Node 4 are incorporated.
When a communication fault occurs in a line between Node 4 and Node 3 in this state of normal operation, Node 3 transmits information of the fault occurrence to Node 4 via Node 2 and Node 1, as illustrated in FIG. 17B. Node 4 receives the information of the fault occurrence, and transmits an optical signal to Node 2, by switching the path so far used to the path at an opposite side (the auxiliary side). Specifically, the optical signal from Node 4 reaches Node 3 via Node 1 and Node 2, and is transmitted to Node 2 after returning from Node 3.
That is, in the network of the BLSR, an optical transmission device achieves switchover control by exchanging the APS byte (K1 byte or K2 byte) between this optical transmission device and the opposite optical transmission device. For example, when an optical transmission device detects a signal failure (SF) or a signal degradation (SD) as a fault at a receiving side, the optical transmission device notifies information of the device itself to the opposite device by using APS byte having stored these pieces of information, thereby achieving switchover to the auxiliary side within a switchover time 50 milliseconds defined by GR-253.
A configuration of an optical transmission device in the network of the BLSR is explained next with reference to FIG. 18. The configuration of an optical transmission device includes the configuration of a centralized CPU device as illustrated in FIG. 18.
As illustrated in FIG. 18, the configuration of the centralized CPU device includes a redundant configuration of a CPU unit that performs monitor control of the entire transmission devices, and a WEST LIU and an EAST LIU as line interface units having an external-line interface function to a currently-used line and an auxiliary line.
The WEST LIU and the EAST LIU include hardware respectively. The hardware receives APS byte from the currently-used line and the auxiliary line, notifies information of an SF and an SD to the CPU unit, and changes a switch according to instructions from the CPU unit. The WEST LIU and the EAST LIU include plural ports, respectively corresponding to the currently-used line and the auxiliary line.
In the configuration of the centralized CPU device, firmware that operates within a CPU of the CPU unit performs switchover control of a switch by aggregating information of the APS byte from the WEST LIU and the EAST LIU.
For example, when the hardware of the WEST LIU as an interface of the currently-used line detects an SF as a switchover cause, the hardware notifies the occurrence of the SF to the firmware of the CPU unit (see (1) in FIG. 18). The firmware of the CPU unit performs an APS determining process (a switchover determining process) based on the received information of the SF and the information of the APS byte from a second LIU (see (2) in FIG. 18), and performs switchover control of the switch to the hardware of the WEST LIU and the hardware of the EAST LIU (see (3) in FIG. 18). As a result, switch switchover as illustrated in FIG. 17B is performed.
However, in the configuration of the centralized CPU device, when the number of ports accommodated in the LIU increases or when plural switchover causes occur simultaneously, quick switchover cannot be performed for a line fault, because APS determining processes in the firmware of the CPU unit becomes congested.
In view of the above problems, there is a configuration of a distributed CPU device as a configuration of an optical transmission device in a network of a BLSR.
That is, as illustrated in FIG. 19, the configuration of the distributed CPU device includes a CPU unit, and the WEST LIU and the EAST LIU having a function of an external-line interface to a currently-used line and an auxiliary line, in a similar manner to that of the configuration of the centralized CPU device. However, CPUs are incorporated in distribution in the WEST LIU and the EAST LIU. Firmware that operates within the CPU of each LIU aggregates information of APS byte, and both pieces of firmware communicate with each other to perform switchover control of a switch by sharing each other's information.
In this case, one of the redundantly configured LIUs needs to perform a switchover determination by referencing information of the APS byte of both the currently-used line and the auxiliary line. A maintenance staff of an optical transmission device sets to the CPU unit that the EAST LIU performs a switchover determination, for example. The EAST LIU receives setting information via firmware within the CPU (a user interface (I/F) unit) of the CPU unit, and the self CPU independently performs a switchover process in the hardware, as a master CPU.
In the configuration of the distributed CPU device, for example, when the hardware of the WEST LIU as the interface of the currently-used line detects an SF as a switchover cause, the hardware notifies the occurrence of the SF to the firmware within the self CPU (see (1) in FIG. 19). The firmware of the WEST LIU notifies the occurrence of the switchover cause to the firmware in the CPU (the master CPU) of the EAST LIU, by communicating with the other firmware (see (2) in FIG. 19). The firmware of the EAST LIU performs an APS determining process (a switchover determining process) based on the switchover cause (the SF) sent from the WEST LIU and based on the information of the APS byte of the EAST LIU (see (3) in FIG. 19).
The firmware of the EAST LIU notifies switchover to the firmware of the WEST LIU as a result of the APS determining process, by communicating with the other firmware (see (4) in FIG. 19). The firmware of the WEST LIU and the firmware of the EAST LIU, respectively perform switchover control to the hardware itself, based on a result of determination by the firmware of the EAST LIU (see (5) in FIG. 19). As explained above, switchover control is performed based on the determining process of the CPU of the EAST LIU which functions as the master CPU, and the switch is changed as illustrated in FIG. 17B, for example.
As a technique of sharing information between CPUs, Japanese Patent Publication No. 06-30002 discloses a programmable controller that enables CPUs to share information by transfer of data from a memory at a master CPU side to a memory at a slave CPU side by direct memory access (DMA).
Similarly, Japanese Laid-open Patent Publication No. 08-202672 discloses a distributed multiprocessing system that enables CPUs to share information by transferring data from a master processor unit to plural slave units via a VERSA Module Eurocard bus (VME bus), between processor units each including a CPU and a memory (between one master unit and plural slave units).
However, the conventional techniques mentioned above have a problem such that, in an LIU that accommodates plural ports, when switchover control is to be performed due to simultaneous occurrence of faults in the plural ports, the processing load of a master CPU becomes high, and the CPU cannot perform a quick switchover process. This problem is briefly explained below with reference to FIGS. 20A and 20B.
That is, in a configuration as illustrated in FIGS. 20A and 20B, when only a master CPU at one-side LIU performs switchover control of “BLSR”, the CPU cannot perform a quick switchover process within 50 milliseconds as defined by GR-253.
For example, as illustrated in FIG. 20A, when LIUs of an optical transmission device (a configuration of a distributed CPU device) that achieves the “BLSR” are redundantly configured such that each LIU accommodates five physical ports, only the master CPU of the LIU at one side needs to perform switchover control based on APS information in a combination of the five physical ports.
As illustrated in FIG. 20B, it is assumed that a ring network configured by 16 nodes (optical transmission devices) achieves “BLSR”. In this case, after a master CPU incorporated in an LIU of node 1 detects information of a signal failure (SF) of an optical signal from Node 16, this master CPU needs to perform plural processes before completing switchover control. That is, the master CPU needs to perform switchover control of itself, to perform switchover control to Node 2 to Node 16, and to receive switchover responses from Node 2 to Node 16. Thus, the master CPU is required to have a high processing capacity.
In the conventional techniques mentioned above, a master CPU of an LIU at only one side can sometimes perform switchover within 50 milliseconds to simultaneous faults of four or a smaller number of ports. However, as illustrated in FIG. 20A, a master CPU of an LIU that accommodates five or more physical ports cannot perform by the master CPU itself a quick switchover process within 50 milliseconds to simultaneous faults of all physical ports.
The present invention has been achieved to solve the problems of the conventional technique described above, and an object of the present invention is to provide an optical transmission device, a switchover processing method, and a switchover processing program which are capable of performing a quick switchover process to simultaneous occurrence of faults in plural ports, dynamically changing a master CPU according to a load status of a CPU, and preventing a main-signal failure time from becoming long.